1. Field of the Invention
The present invention relates to an adder, in particular, to a carry selecting system type adder.
2. Discussion of the Background
As a conventional adder, a ripple carry type is known. In this adder, the adding of an augend and an addend for each bit is executed after receiving a carry input signal from an adding circuit disposed in a preceding stage.
However, in this adder, until the addition of the most significant bit is executed, due to delay of carry propagation, the entire processing performance of the microprocessor is deteriorated. To prevent the delay of the carry propagation, it is known that a carry selecting system type adder executes an addition corresponding to two carry inputs beforehand.
FIG. 9 is a schematic diagram showing the construction of the carry selecting system type adder described in, for example, Japanese Patent Laid-Open Publication No. Hei 5-6263. In the drawing, the carry selecting system type adder is constructed of an AND device 1, exclusive OR devices 2-4, an OR device 5, a carry generating signal circuit 6, and a carry propagating signal circuit 7. In this adder relating to an addition of the augend A and the addend B, a sum (sum S0) in the case that the carry input value is "0" and a sum (sum S1) in the case that the carry input value is "1" are simultaneously calculated by the OR device 5 and the exclusive OR devices 3 and 4 disposed in one adder.
FIG. 10 is a detailed circuit diagram showing a 4-bit carry selecting system type adder using the adder shown in FIG. 9. In FIG. 10, the 4-bit carry selecting system type adder is constructed of AND devices 8-14, exclusive OR devices 15-26, OR devices 27-30, first selector circuits 31-34, and second selector circuits 35-38. The carry generating signal circuit 6 and the carry propagating signal circuit 7 shown in FIG. 9 are constructed of the first selector circuits 31 to 33 and the AND devices 12 to 14 shown in FIG. 10. One of two sums (sum S0 and sum S1) generated at the same time is selected by the second selectors 34 to 38 based on the carry input value, and output as carry outputs SUM0 to SUM3. Thus, the delay of carry propagation is removed.
Since the conventional adder is constructed as described above, the following problems take place.
The improvement of the processing performance of adders contributes to one factor in the improvement of the processing performance of a microprocessor incorporating the adder. To construct a high speed adder, a parallel process is effectively used. However, the parallel process requires an increase of the amount of hardware, thereby increasing the area of the microprocessor and adversely affecting the layout of the existing chips. Thus, it is important to design the adder so that the amount of hardware required is reduced.
In the above-described adder, exclusive OR devices and AND devices are used so as to calculate added results in the case that the carry input is "0" and in the case that the carry input is "1" at the same time. Thus, the amount of hardware required becomes large, and thereby power consumption increases. The chip area and power consumption of microprocessors are required to decrease, year by year. Thus, the amount of hardware and power consumption of the adder that is an essential portion of a calculating process of the microcomputer must be further decreased.